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A developer has shared a version of the Project Oberon system that runs on RISC-V hardware, replacing the original RISC-5 architecture. This marks a significant porting effort and demonstrates the system’s adaptability.
A developer has publicly shared a version of the Project Oberon operating system that runs on RISC-V hardware, replacing the original RISC-5 architecture. This development highlights the system’s portability and ongoing interest in open hardware platforms, making it relevant for enthusiasts and researchers in operating systems and processor architectures.
The developer, whose post appeared on Show HN, demonstrated a working port of the Project Oberon System on a RISC-V processor. The port involves adapting the system’s low-level code and drivers to support RISC-V’s instruction set, which differs significantly from RISC-5. The project is still in early stages but successfully boots and performs basic operations on the new architecture, according to the post. This effort is notable because Project Oberon was originally designed for a custom RISC-5 processor, developed by Niklaus Wirth and his team at ETH Zurich in the 1980s, emphasizing simplicity and efficiency.Implications for Open Hardware and OS Portability
This port demonstrates that legacy operating systems like Oberon can be adapted to modern open hardware platforms such as RISC-V. It underscores the potential for educational and research projects to leverage open-source hardware and software, fostering innovation outside proprietary systems. For the broader community, it signals ongoing interest in revisiting classic systems with contemporary architectures, potentially inspiring further porting efforts and new implementations.
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- MCU Chip: ESP32-C3 32-bit RISC-V, 160 MHz
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- Compatibility: Supports Arduino, MicroPython, PlatformIO, and more
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Background on Project Oberon and RISC-V Compatibility Efforts
Project Oberon, developed in the 1980s by Niklaus Wirth and colleagues, was originally designed for a custom RISC-5 processor, emphasizing simplicity, efficiency, and minimal hardware requirements. Over the years, the system has been influential in educational settings and in the development of minimalistic operating systems. RISC-V, an open-source instruction set architecture, has gained popularity for its flexibility and openness, prompting various efforts to port existing systems to it. Prior to this development, there have been several projects aiming to adapt other operating systems and tools to RISC-V, but a port of Oberon is considered notable due to its unique architecture and design principles.
“This port is still early but demonstrates that Oberon can run on RISC-V hardware, opening doors for further development and experimentation.”
— Developer posting on Show HN
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Extent of System Functionality and Stability on RISC-V
It is not yet clear how fully functional the RISC-V port is beyond basic booting and initial operations. The stability, performance, and compatibility with all Oberon features remain unconfirmed, and further testing is needed to assess its readiness for practical use or development.
ESP32-C5 5GHz/2.4GHz Dual-Band Wi-Fi 6 Dev Board, ESP32-C5-WROOM-1 Module
- Processor: RISC-V 32-bit, up to 240MHz
- Memory: 384KB SRAM, 16MB Flash, 8MB PSRAM
- Wi-Fi Support: Dual-band Wi-Fi 6 (2.4GHz/5GHz)
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Next Steps in Developing and Testing the RISC-V Port
The developer plans to continue refining the port, adding support for more hardware features, and testing stability under various workloads. Community involvement and collaboration may accelerate development, and future updates are expected to address current limitations. Additionally, more comprehensive benchmarking and documentation are anticipated to support wider adoption and experimentation.
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- WiFi 6 Module: High-speed, low-latency network connectivity
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Key Questions
What is Project Oberon?
Project Oberon is an operating system and programming environment developed in the 1980s by Niklaus Wirth and colleagues at ETH Zurich, originally designed for a custom RISC-5 processor.
Why is porting Oberon to RISC-V significant?
It demonstrates the adaptability of the system to modern, open-source hardware architectures, supporting educational and research projects outside proprietary environments.
Is the RISC-V version fully functional?
No, the port is still in early development. It currently boots and performs basic operations, but full functionality and stability are still being worked on.
Who developed the RISC-V port?
The port was created and shared by an independent developer on Show HN, with ongoing development efforts.
What are the implications for the open hardware community?
This effort showcases the potential for porting legacy systems to open architectures, encouraging further experimentation and innovation in open-source hardware and software.
Source: hn
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